With recent progresses of digital technologies, electronic devices such as portable information devices and information home appliances have been developed to provide enhanced functionalities. Because of this, there have been increasing demands for an increased capacity of a non-volatile memory device, a reduced write electric power in the non-volatile memory device, a reduced write/read time in the non-volatile memory device, and longer life of the non-volatile memory device.
Under the circumstances in which there are such demands, miniaturization of the existing flash memory using a floating gate has been progressing.
In the case of a non-volatile semiconductor memory element (resistance variable memory, hereinafter referred to as ReRAM) including as a memory section a variable resistance element which changes its resistance values retained stably, by application of voltage pulses, a memory cell can be implemented with a simple structure. Therefore, further miniaturization, a higher-speed, and lower electric power consumption of the non-volatile semiconductor memory element are expected.
As a variable resistance layer, there are proposed a nickel oxide layer (NiO), a vanadium oxide layer (V2O5), a zinc oxide layer (ZnO), a niobium oxide layer (Nb2O5), a titanium oxide layer (TiO2), a tungsten oxide layer (WO3), a cobalt oxide layer (CoO), etc. (see Patent Literature 1). It is known that each of these transition metal oxide layers exhibits specific resistance values when voltages or currents which are equal to or greater than thresholds are applied thereto and retain the specific resistance values until voltages or currents are newly applied thereto. These transition metal oxide layers have a feature that they can be manufactured using the existing semiconductor manufacturing process steps substantially without modifying them.
There has been proposed a cross-point memory array having a configuration in which memory cell arrays are stacked together on a conventional CMOS circuit (see Patent Literature 2).